Document ID: TOS-DIAG-REF-002 Revision: 1.0 Author: ThisOldScot
Section_1: Overview#
In the Borders Lab, we define the Reset Signal as the command that tells the CPU to “wake up” and look at the first instruction in the BIOS. Without a clean, timed reset pulse, a CPU exists in a state of logical paralysis.
When a system boots to a “Black Screen” but has healthy 5V/3.3V rails and a functioning Master Clock (see TOS-DIAG-REF-001), the Reset Circuit is the primary forensic suspect.
Section_2: Essential Equipment & Setup#
| Component | Spec | Function |
|---|---|---|
| Oscilloscope | 2-Channel | Monitoring the relationship between Power-on and Reset. |
| Logic Probe | Pulse Detection | Quick “Go/No-Go” verification of the Reset pin state. |
| Schematic | CPU Pinout | Identifying the /RESET or RST pin (e.g., Pin 18 on a Z80). |
Section_3: The Reset Protocol#
STAGE_3: 01 // Understanding “Active Low” Logic#
Most retro CPUs (68000, Z80, 6502) utilize Active Low reset signals, designated with a bar over the name or a forward slash (/RESET).
- The Logic: At idle (running), the pin must stay High (5V). To trigger a reset, the pin must momentarily drop to Low (0V).
- The Failure: If the pin is stuck at 0V, the CPU is in a “Permanent Reset” state.
STAGE_3: 02 // The Power-On Reset (POR) Timing#
The reset signal must not go High the instant power is applied. It must stay Low for a few milliseconds (usually 10ms – 100ms) to allow the voltage rails and the Master Clock to stabilize.
- The Test: Set your Oscilloscope to Single Trigger mode.
- Analysis: You should see the 5V rail rise, followed shortly by the Reset line “flipping” from 0V to 5V. If they rise at the exact same time, the CPU may attempt to read the BIOS before it is ready, leading to a crash.
STAGE_3: 03 // The Reset IC vs. RC Circuit#
- Discrete (RC): Older systems (NES/Atari) often use a simple Resistor-Capacitor circuit. A dried-out capacitor here will cause intermittent boot failures.
- Integrated (Reset IC): Newer systems (Game Gear, Saturn) use a dedicated chip (e.g., the PST518). These monitor the voltage and only release the reset line once the rail hits a specific threshold (e.g., 4.2V).
Section_4: CPU “Halt” and “Wait” States#
A secondary forensic layer involves the HALT pin.
- Diagnosis: If the Reset line is High (correct), but the CPU still isn’t processing data, check the
/HALTpin. - Implication: If a CPU detects a bus error (e.g., a short on a data line), it will pull its own HALT line Low. This is the CPU’s way of “protecting” itself from invalid data.
Section_5: Technical Warning#
Safety_Warning
BUS CONTENTION ALERT: Never manually force a Reset pin to 5V by bridging it to a power rail. If the Reset IC is trying to pull the line Low while you are forcing it High, you will create a localized short-circuit that can destroy the Reset IC or the CPU’s internal logic gate. Always use a 1k Ohm resistor as a “pull-up” for testing.
Section_6: Practical Application: Game Gear “One-Second” Reset#
If a Game Gear is recapped but still fails to boot:
- Locate the PST518 Reset IC near the power connector.
- Probe Pin 1 (Reset Out) during power-on.
- If the pin never reaches 5V, the IC is failed or the 5V rail has too much ripple (noise) for the IC to authorize a boot.
- The Fix: Replacing this $1 component often restores a “dead” motherboard that has been written off as a failed ASIC.