Document ID: TOS-LOG-REF-004 Revision: 1.0 Author: ThisOldScot
Section_1: Overview#
At the high frequencies used by 16-bit and 32-bit consoles, electricity does not move “instantly.” Propagation Delay is the time it takes for a signal to travel through a logic gate or across a PCB trace. When we add modern mods (like HDMI taps or ODEs), we risk introducing Clock Skew—where two signals that should arrive at the same time are out of sync.
In the Borders Lab, we use high-bandwidth oscilloscopes to measure these nanosecond delays to prevent “Race Conditions” that cause graphical tearing or data corruption.
Section_2: Technical Definitions#
- Propagation Delay ($t_{pd}$): The time from the input reaching 50% voltage to the output reaching 50% voltage.
- Clock Skew ($t_{skew}$): The difference in arrival time of a single clock edge at different points on the board.
- Setup Time ($t_s$): The minimum time data must be stable before the clock edge arrives.
Section_3: The Timing Diagnostic Protocol#
To verify if a mod is causing sync issues, follow the Delta-T Sweep:
STAGE_3: 01 // The Dual-Probe Baseline#
Place Probe 1 on the Master Clock crystal and Probe 2 on the CPU Clock input pin.
STAGE_3: 02 // Measuring the Phase Shift#
On the Oscilloscope (TOS-DIAG-001), use the “Delay” or “Delta” measurement tool.
- Standard: In a Sega Saturn, the delay between the Master Clock and the VDP clock should be less than 5ns.
- Failure: If the delay is >10ns, the video chips will miss data cycles, resulting in “sparklies” on the screen.
STAGE_3: 03 // Identifying “Gate Lag”#
If you have replaced a 74LS series chip with a 74HC series, the speed difference can crash the bus.
- Forensic Clue: HC logic is faster than LS. If the logic state changes too early, the CPU might read the bus while the data is still “settling,” leading to random memory errors.
Section_4: Correcting Skew: The “Length Matching” Rule#
Signals travel at roughly 6 inches per nanosecond on a standard FR-4 PCB.
- The Fix: If an HDMI mod is out of sync, ensure all wires in the data bus (R0-R7, G0-G7, B0-B7) are the exact same length. Even a 2-inch difference in wire length can cause a 300ps skew, which is enough to degrade high-definition signals.
Section_5: Technical Warning#
Safety_Warning
CAPACITIVE LOADING ALERT: Probing a high-speed clock line with a standard 1x probe adds significant “Capacitance” (pF). This capacitance slows down the signal rise-time, artificially increasing the propagation delay you are trying to measure. Always use 10x Probes for timing analysis.
Section_6: Practical Application: N64 Digital Sync Drops#
If an N64 HDMI mod experiences frequent “No Signal” drops:
- Probe the DCLK (Data Clock) line.
- Check for “Ringing” or overshoot on the pulse edges.
- The Fix: Add a 22-ohm to 47-ohm series resistor at the source of the clock. This dampens the signal reflections and “sharpens” the timing, eliminating sync drops.