Document ID: TOS-LOG-REF-003 Revision: 1.0 Author: ThisOldScot
Section_1: Overview#
In many 90s consoles and arcade boards (Capcom CPS1/2, Neo-Geo), “Custom Glue Logic” was handled by PAL (Programmable Array Logic) or GAL (Generic Array Logic) chips. These chips are the precursor to FPGAs. Because they are programmed with proprietary equations, a failed GAL often results in a “Dead” board that cannot be fixed with standard off-the-shelf parts.
In the Highlands Lab, we utilize CPLD (Complex Programmable Logic Devices) to replicate these failed chips, ensuring the longevity of high-value arcade and console hardware.
Section_2: Logic Families in Transition#
| Device Type | Voltage | Re-programmable? | Status |
| PAL16R8 / 20R8 | 5V | No (One-time) | Legacy (Common failure point). |
| GAL16V8 / 22V10 | 5V | Yes | Direct replacement for PALs. |
| XC9500 (CPLD) | 5V/3.3V | Yes (Flash) | The modern standard for replication. |
| EPM7000 (CPLD) | 5V | Yes | High-speed, high-density logic. |
Section_3: The Extraction & Reverse Engineering Protocol#
If the equations for a proprietary chip are not archived, we must “Sniff” the logic.
STAGE_3: 01 // Logic State Mapping#
Attach a Logic Analyzer (TOS-DIAG-003) to every pin of a known-working chip. Record the inputs and the resulting outputs during a full boot cycle.
STAGE_3: 02 // Boolean Synthesis#
Use the captured data to derive the Boolean Equations (e.g., Output = (A AND B) OR NOT C).
STAGE_3: 03 // Compiling the JEDEC File#
Input the equations into a compiler (like WinCUPL for GALs or Quartus for Altera CPLDs) to generate the binary “fuse map.”
Section_4: Programming & Installation#
- Hardware Handshake: Connect the CPLD to the JTAG Programmer (Xilinx Platform Cable or Altera USB-Blaster).
- Verification: Perform a “Blank Check” before flashing the new logic map.
- The Socket Rule: Never solder a CPLD directly to a vintage board during R&D. Always use a high-quality Machined Pin Socket to allow for easy logic updates if bugs are found.
Section_5: Technical Warning#
Safety_Warning
SECURITY BIT ALERT: Many original arcade PALs have a “Security Bit” set at the factory. This prevents the chip from being read by a programmer. If the security bit is active, the only way to replicate the chip is through the Logic Sniffing Protocol described in Section 3. Attempting to “Force Read” a secured chip can result in internal logic corruption.
Section_6: Practical Application: Neo-Geo Custom IC Failure#
The Neo-Geo MVS uses several custom “PRO-XXX” chips for address decoding. When these fail:
- We desolder the failed ASIC.
- We install a custom PCB interposer containing a Xilinx XC9572 CPLD.
- We flash the “PRO-Decoding” equations to the CPLD.
- The Result: A perfectly functional Neo-Geo restored with modern, reliable logic.